摘 要
在現(xiàn)代先進的電子系統(tǒng)的前端和后端都將應(yīng)用到A／D轉(zhuǎn)換器，以改善數(shù)字處理技術(shù)的性能。在各種A／D轉(zhuǎn)換器中，逐次逼近型A／D轉(zhuǎn)換器是采樣率低于5 Msps(每秒百萬次采樣)的中等至高等分辨率應(yīng)用的常見結(jié)構(gòu)。由于逐次逼近型A／D轉(zhuǎn)換器具有低功耗、小尺寸的特點，因此有很寬的應(yīng)用范圍。 本文設(shè)計的8位逐次逼近A／D轉(zhuǎn)換器，采用了以D／A轉(zhuǎn)換器、比較器和帶隙基準(zhǔn)模塊為主體的結(jié)構(gòu)，通過各個模塊的優(yōu)化設(shè)計，得到了可在4.5V-5.5V單電源電壓下工作的中速、低功耗8位逐次逼近A／D轉(zhuǎn)換器。 D／A轉(zhuǎn)換器模塊采用了擴展分辨率的方法，將電阻分壓和電容分壓相結(jié)合，得到了不同縮放方式的DAC組合，擴展D／A轉(zhuǎn)換器分辨率，也提高了轉(zhuǎn)換速度。比較器模塊采用了三級比較器通過電容耦合級聯(lián)的方式來實現(xiàn)，具有高增益的特點，結(jié)果所設(shè)計的比較器既滿足了高速比較的要求，又有效降低了功耗。最后，在A／D轉(zhuǎn)換器中基準(zhǔn)電壓模塊也是一個很重要的組成部分，它直接關(guān)系A(chǔ)／D轉(zhuǎn)換器的精度。本文中自主設(shè)計的帶隙基準(zhǔn)電路具有很高的抗電源電壓波動和抗溫度變化的能力，溫度在-50℃-100℃、電源電壓在1.6V-9.7V范圍內(nèi)變化時能使輸出保持在1.246V。 應(yīng)用Cadence spectre采用CSMC 0.6μm CMOS Nwell工藝庫對電路性能進行驗證。仿真結(jié)果表明，設(shè)計的高速比較器、帶隙基準(zhǔn)電路和D／A轉(zhuǎn)換器滿足8位A／D轉(zhuǎn)換的要求。
Abstract
In the front and the end of the advanced electronics systems, analog to digital converters (A/D converters) are applied to improve the performance of the digital processing technique. Of all kinds of A/D converters, successive approximation (SAR)A/D converters are frequently the architecture of choice for medium-to-high-resolution applications with sample rates under 5 mega samples per second (Msps). Because of providing low power consumption as well as a small scale factor, SAR A/D converters have a wide variety of applications.A 8-bit medium speed, low power A/D designed in this paper, is composed of digital-analog (D/A) converters, comparators ,bandgap and so on. By optimizing the performances of every module, it can operate well from from a signal 4.5V to 5.5V power supply.In D/A coverter module, in order to extend the resolution of D/A converter, the combination of differently scaled DACs is designed. A charge scaling D/A converter with capacitor voltage divider and resistance divider is designed, which extends the resolution of a parallel D/A converter as well as improve speed rate greatly. The comparator has the character of high gain with the structure of three-stage coupled capacitance, which reduces power consumption as well as satisfies the requirement of high speed comparator. Bandgap voltage circuits is an important module for A/D converter, which affects the accuracy of A/D converter. The bandgap designed in this paper has the capability of anti-fluctuation of power supply and temperature. It can work from a signal 4.5V to 5.5V power supply and from -50℃ to 100℃ temperature and always get 1.246V output voltage.By using the CSMC 0.6 μm CMOS Nwell technology, the circuits are verified in circumstances of Cadence spectre with Unix operating system. The simulation shows that the high speed comparator, the D/A converter and the bandgap meet the requirements of the 8-bit A/D converter, and the SAR A/D converter can work well.





























目 錄
摘 要 I
Abstract I
目 錄 III
前言 IV
第一章 緒論 1
第二章總體方案 2
2.1 方案選擇 2
2.2 方案設(shè)計的基本思路 2
第三章 硬件設(shè)計與分析 4
3.1 常用單片機的特點比較及本設(shè)計單片機的選擇 4
3.2 AT89S52單片機性能簡介 4
3.3 常用顯示簡介 7
3.4 A/D轉(zhuǎn)換芯片AD0804 11
3.5 采樣保值電路 13
第四章 軟件設(shè)計與分析 16
4.1系統(tǒng)軟件設(shè)計主流程圖 16
4.2系統(tǒng)軟件的A/D轉(zhuǎn)換流程圖 17
4.3 顯示流程 18
第五章 調(diào)試與分析 19
5.1 樣機的裝接分析與調(diào)試 19
5.2 多功能版的裝接分析與調(diào)試 23
第六章 總論 26
6.1 結(jié)論與展望 26
6.2 單片機的發(fā)展趨勢 26
致 謝 28
參考資料 29
附錄 30