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基于usb20的虛擬數(shù)字存儲示波器硬件系統(tǒng)設(shè)計(jì).doc

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基于usb20的虛擬數(shù)字存儲示波器硬件系統(tǒng)設(shè)計(jì),基于usb20的虛擬數(shù)字存儲示波器硬件系統(tǒng)設(shè)計(jì)摘 要在計(jì)算機(jī)科學(xué)技術(shù)和測試技術(shù)持續(xù)發(fā)展的基礎(chǔ)上,根據(jù)實(shí)際需求,產(chǎn)生了一種新型的測量儀器——虛擬儀器,本文設(shè)計(jì)的基于usb2.0的虛擬示波器正是虛擬儀器的一種,具有功能強(qiáng)、速度高、測量準(zhǔn)確、實(shí)時性好、結(jié)構(gòu)輕巧、人機(jī)界面友好及操作簡單等優(yōu)點(diǎn),滿足測量發(fā)展的需要,應(yīng)用前景非常廣...
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基于USB20的虛擬數(shù)字存儲示波器硬件系統(tǒng)設(shè)計(jì)

 摘  要
在計(jì)算機(jī)科學(xué)技術(shù)和測試技術(shù)持續(xù)發(fā)展的基礎(chǔ)上,根據(jù)實(shí)際需求,產(chǎn)生了一種新型的測量儀器——虛擬儀器,本文設(shè)計(jì)的基于USB2.0的虛擬示波器正是虛擬儀器的一種,具有功能強(qiáng)、速度高、測量準(zhǔn)確、實(shí)時性好、結(jié)構(gòu)輕巧、人機(jī)界面友好及操作簡單等優(yōu)點(diǎn),滿足測量發(fā)展的需要,應(yīng)用前景非常廣闊。
本文緊緊圍繞虛擬示波器的硬件結(jié)構(gòu)設(shè)計(jì)這一課題展開,主要研究以下內(nèi)容:
1.模擬通道電路設(shè)計(jì)。依據(jù)信號的流向,給出了耦合方式選擇電路、無源衰減網(wǎng)絡(luò)、阻抗變換電路、可程控固定倍率衰減、信號放大電路以及觸發(fā)源選擇電路和觸發(fā)脈沖產(chǎn)生電路等信號調(diào)理通道和觸發(fā)通道中幾個主要硬件部分的設(shè)計(jì)方案。
2.?dāng)?shù)據(jù)采集系統(tǒng)設(shè)計(jì)。采用ADC+FPGA+DSP的系統(tǒng)構(gòu)架,以多片低速ADC器件并行完成1GSPS實(shí)時采樣率的技術(shù)指標(biāo),對采集數(shù)據(jù)運(yùn)用并行分相存儲技術(shù)緩存,由DSP處理器對采樣數(shù)據(jù)進(jìn)行實(shí)時處理,大大減少通訊接口壓力。
3.USB接口模塊設(shè)計(jì)及電源設(shè)計(jì)。選用USB2.0接口芯片設(shè)計(jì)接口電路用于連接儀器硬件和個人電腦,保障數(shù)據(jù)傳輸?shù)乃俣群头€(wěn)定性。電源模塊的設(shè)計(jì)是為系統(tǒng)正常穩(wěn)定工作提供一個合理的電源系統(tǒng),其本身的質(zhì)量直接影響著系統(tǒng)性能。
4.電磁兼容設(shè)計(jì)。從布局布線、電源及接地等方面分析了高速PCB布板中電磁兼容的設(shè)計(jì),最大程度地降低干擾等對性能的影響。
5.最后,給出實(shí)驗(yàn)結(jié)果并結(jié)合調(diào)試工作,列舉了調(diào)試過程中遇到的突出問題,并對解決過程給予描述,目的是提供一種分析問題、解決問題的思路和方法。

關(guān)鍵詞:虛擬示波器,數(shù)據(jù)采集,交替采樣,USB2.0,電源
 
Abstract
Based on the sustainable development of computer science and testing technology, virtual instruments, a new type of measuring instruments, emerge to meet the actual demands. The virtual oscilloscope, which is designed on the basis of USB2.0, is one kind of virtual instruments. Being characteristic of powerful functions, high speed, accurate measurement, real time, light structure, friendly man-machine interface and simple operation, it meets the needs of measurement development with a wide range of applications.
This paper mainly focuses on hardware structure design of the virtual oscilloscope. The research has been carried out in the following aspects:
1. Circuit design of the analog channel. According to signal flow, the paper presents a design proposal for several major hardware parts in signal conditioning channel and trigger channel, including circuit selection by coupling modes, passive attenuation network, impedance converting circuit, programmable fixed rate attenuation, signal amplifier and trigger source selection circuit and the trigger pulse generation circuits.
2. Data Acquisition System. With the adoption of the frame structure of ADC + FPGA + DSP, Parallel sampling module completes 1GSPS data acquisition system with multi-chip low-speed ADC devices, then the data processing is completed by the DSP processor, and it can significantly reduce the communication interface pressure.
3. USB interface module design and power design. USB2.0 interface chip is selected to design the interface circuit for connecting instrument hardware and personal computers and ensuring data transmission speed and stability. Power module is designed to provide a reasonable power system so as to guarantee the normal and stable operation of the whole system. Its own quality directly affects the system performance.
4. EMC Design. From the layout, power supply and ground, the paper analyzes the design of electromagnetic compatibility in high-speed PCB layout in order to minimize the interference on the performance.
5. Finally, Experimental results are presented and in combination with the debugging, the paper cites some serious problems and describes the resolving process with an aim to provide an idea and a method for analyzing and solving the problems.

Keywords: Virtual oscilloscope, data acquisition, alternative sampling, USB2.0, power supply


 
目  錄
第一章 引言 1
1.1 虛擬儀器概述 1
1.2 虛擬儀器發(fā)展?fàn)顩r 2
1.3 選題背景及選題意義 3
1.4 課題目標(biāo)及論文主要研究內(nèi)容 3
第二章 虛擬數(shù)字存儲示波器硬件系統(tǒng)總體方案 5
2.1 總體設(shè)計(jì)方案 5
2.2 系統(tǒng)結(jié)構(gòu) 6
2.2.1 模擬通道 6
2.2.2 數(shù)據(jù)采集 7
2.2.3 數(shù)據(jù)處理及存儲 7
2.2.4 通用串行總線 7
2.2.5 電源模塊 8
第三章 硬件系統(tǒng)設(shè)計(jì) 9
3.1 模擬通道電路設(shè)計(jì) 9
3.2 數(shù)據(jù)采集及處理系統(tǒng)設(shè)計(jì) 16
3.2.1 關(guān)鍵器件的選型 16
3.2.2 并行采集電路 20
3.2.3高速采樣時鐘 25
3.2.4 數(shù)據(jù)并行存儲 28
3.3 FPGA及外圍電路 36
3.4 DSP處理電路設(shè)計(jì) 38
3.4.1 存儲器擴(kuò)展電路 38
3.4.2  JTAG接口電路 40
3.5 USB2.0硬件設(shè)計(jì) 41
3.5.1 USB總線特性 41
3.5.2 USB接口芯片 42
3.5.3 USB接口電路的實(shí)現(xiàn) 44
3.6 電源模塊設(shè)計(jì) 46
3.6.1 DC-DC電壓轉(zhuǎn)換 46
3.6.2 LDO低壓差線性穩(wěn)壓 50
3.7電磁兼容設(shè)計(jì) 52
3.7.1布局布線電磁兼容設(shè)計(jì) 52
3.7.2電源電磁兼容設(shè)計(jì) 54
3.7.3接地電磁兼容設(shè)計(jì) 55
第四章 系統(tǒng)調(diào)試與驗(yàn)證 57
4.1 電源模塊的調(diào)試 57
4.2 FPGA的調(diào)試 59
4.3 DSP及ADC的調(diào)試 61
4.4 通道部分的調(diào)試 62
4.5 測試驗(yàn)證效果 63
第五章 結(jié)束語 67
致 謝 68
參考文獻(xiàn) 69
附 錄 71