論文標準WORD格式排版 26頁

摘 要：本文通過運用EDA技術，采用VHDL語言和原理圖輸入法編輯文件,采用移項相加原理對八位乘法器進行了設計，經(jīng)過編譯、化簡、分割、綜合、優(yōu)化、布局、布線、仿真及測試,綜合后下載到EPM7128SLC84-15測試最終得到所要設計的八位乘法器.它能進行八位數(shù)據(jù)之間的相乘運算，并且通過數(shù)碼管把結(jié)果顯示出來.
關鍵詞：電子設計自動化，硬件描述語言，乘法器

Design of eight hardware multiplication machines
Abstract: This text passes uses the usage EDA technique, the adoption VHDL language and the principle diagram input method edit a document, adopting to move an item to add principle mutually to eight multiplication machines to carry on a design, has been editted and translate,turn Chien,partition,synthesize,excellent turn,set up,cloth line,imitate really and test,
After the synthesis downloading to the EPM7128SLC84-15 board for tests,Finally obtained eight multipliers which was requested to design. It can carry on the eight-digit number according to seemultiplications the operation,and demonstrate the result through the digital tube.

Key words：　EDA， HDL，multiplication machine.

目 錄
摘 要……………………………………………………………………………I
Abstract…………………………………………………………………………II
第1章 緒論……………………………………………………………………2
1.1課題背景……………………………………………………………………2
1.2 Max+PlusII簡介…………………………………………………………… 3
1.3設計目的……………………………………………………………………3
1.4本章小結(jié)……………………………………………………………………3
第2章 硬件乘法器的設計的方案……………………………………………4
2.1乘法器的算法原理…………………………………………………………4
2.2設計原理……………………………………………………………………5
2.3 本章小結(jié)…………………………………………………………………...6
第3章 硬件乘法器的軟件實現(xiàn)………………………………………………7
3.1結(jié)構圖………………………………………………………………………7
3.2乘法器的底層文件設計……………………………………………………7
3.3乘法器的頂層文件設計………………………………………………… .14
3.4 譯碼顯示……………………………………………………………… …16
3.5 本章小結(jié)……………………………………………………………… …18
第4章 硬件乘法器的硬件實現(xiàn)……………………………………………..19
結(jié)論……………………………………………………………………………21
致謝……………………………………………………………………………22
心得體會………………………………………………………………………23
參考文獻………………………………………………………………………24